Program

Following is the program schedule for the 7th International Symposium on Networks-on-Chip (NOCS’13).

(PDF of the program schedule can be downloaded here.)


Sunday, April 21, 2013 – Tutorial Day

Tutorial Location: BYENG 210, 699 S. Mill Ave., Tempe, AZ, 85281 (5 mins walk from NOCS site)

8.45 -- 12.00 Tutorial 1
MILLIMETER (mm)-WAVE WIRELESS NoC AS INTERCONNECTION BACKBONE FOR MULTICORE CHIPS: PROMISES AND CHALLENGES
Partha Pratim Pande, Washington State University, Pullman, WA;
Manos M. Tentzeris, Georgia Institue of Technology, Atlanta, GA;
Deukhyoun Heo, Washington State University, Pullman, WA.
12.00 -- 1.30 Lunch
1.30 -- 4.45 Tutorial 2
AUTOMATIC DEADLOCK VERIFICATION IN WORMHOLE NETWORK-ON-CHIPS
Julien Schmaltz and Freek Verbeek
Open University of the Netherlands, Heerlen, The Netherlands.
6.30 -- 8.30 Welcome reception (Courtyard West, Tempe Mission Palms Hotel)


Monday April 22, 2013 – NOCS Day 1

8.15 -- 8.30 Welcome Address
8.30 -- 9.30 Keynote Address
HETEROGENEOUS INTERCONNECTS FOR HETEROGENEOUS COMPUTING
Professor Luca Benini
University of Bologna, Bologna, Italy.

Abstract
Keynote Address Slides
9.30 -- 9.45 Coffee Break
9.45 -- 11.05 Session 1: Emerging Technology: Optics, Wireless and 3D
Session Chair: Ajay Joshi, Boston University.
  1. ENERGY-EFFICIENT ADAPTIVE WIRELESS NOCS ARCHITECTURE
    Dominic DiTomaso, Avinash Kodi, David Matolak, Savas Kaya, Soumyasanta Laha and William Rayess
    Presentation Slides

  2. PROBE: PREDICTION-BASED OPTICAL BANDWIDTH SCALING FOR ENERGY-EFFICIENT NOCS
    Li Zhou and Avinash Kodi
    Presentation Slides

  3. LUMINOC: A POWER-EFFICIENT, HIGH-PERFORMANCE, PHOTONIC NETWORK-ON-CHIP FOR FUTURE PARALLEL ARCHITECTURES (S)
    Mark Browning, Cheng Li, Paul Gratz and Samuel Palermo
    Presentation Slides

  4. 3D LOGARITHMIC INTERCONNECT: STACKING MULTIPLE L1 MEMORY DIES OVER MULTI- CORE CLUSTERS (S)
    Erfan Azarkhish, Igor Loi and Luca Benini
    Presentation Slides

  5. LEVERAGING THE GEOMETRIC PROPERTIES OF ON-CHIP TRANSMISSION LINE STRUCTURES TO IMPROVE INTERCONNECT PERFORMANCE: A CASE STUDY IN 65NM (S)
    Shomit Das, Georgios Manetas, Kenneth Stevens and Roberto Suaya
11.05 -- 12.00 Poster Session I + Coffee Break
12.00 -- 1.30 Lunch
Café Boa, 398 S Mill Ave, Tempe, AZ 85281. (We will walk from the meeting room)
1.30 -- 3.05 Session 2: Routing Algorithms
Session Chair: Danella Zhao, University of Louisiana at Lafayette
  1. GCA: GLOBAL CONGESTION AWARENESS FOR LOAD BALANCE IN NETWORKS-ON-CHIP
    Mukund Ramakrishna, Paul Gratz and Alexander Sprintson
    Presentation Slides

  2. HEADFIRST SLIDING ROUTING: A TIME-BASED ROUTING SCHEME FOR BUS-NOC HYBRID 3-D ARCHITECTURE
    Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi and Hideharu Amano

  3. A GREEDY APPROACH FOR LATENCY-BOUNDED DEADLOCK-FREE ROUTING PATH ALLOCATION FOR APPLICATION-SPECIFIC NOCS
    Amit Verma, Pritpal Singh Multani, Daniel Mueller-Gritschneder, Vladimir Todorov and Ulf Schlichtmann

  4. A DEADLOCK-FREE ROUTING ALGORITHM REQUIRING NO VIRTUAL CHANNEL ON 3D-NOCS WITH PARTIAL VERTICAL CONNECTIONS (S)
    Jinho Lee and Kiyoung Choi
    Presentation Slides

  5. SNET, A FLEXIBLE, SCALABLE NETWORK PARADIGM FOR MANYCORE ARCHITECTURES (S)
    Celine Azar, Stephane Chevobbe, Yves Lhuillier and Jean-Philippe Diguet
3.05 -- 4.00 Poster Session II + Coffee Break
4.00 -- 5.00 Session 3: Fault Tolerance and Reliability
Session Chair: Zhonghai Lu, KTH
  1. AN NOC AND CACHE HIERARCHY SUBSTRATE TO ADDRESS EFFECTIVE VIRTUALIZATION AND FAULT-TOLERANCE
    Mario Lodde and José Flich
    Presentation Slides

  2. MINIMAL-PATH FAULT-TOLERANT APPROACH USING CONNECTION-RETAINING STRUCTURE IN NETWORKS-ON-CHIP
    Masoumeh Ebrahimi, Masoud Daneshtalab, Juha Plosila and Hannu Tenhunen

  3. BACKWARD PROBING DEADLOCK DETECTION FOR NETWORKS-ON-CHIP (S)
    Yean-Ru Chen, Zi-Rong Wang, Pao-Ann Hsiung, Sao-Jie Chen and Meng-Hsun Tsai
5.00 -- 5.45 Poster Session III + Coffee Break


Tuesday April 23, 2013 – NOCS Day 2

8.30 -- 9.30 Keynote Address
UNDERSTANDING NETWORKS-ON-CHIP: A DECADE AND BEYOND
Professor Radu Marculescu
Carnegie Mellon University, Pittsburgh, PA.

Abstract
Keynote Address Slides
9.30 -- 9.45 Coffee Break
9.45 -- 11.10 Session 4: Simulation and Modeling
Session Chair: Sudeep Pasricha, Colorada State University.
  1. SCALABLE PARALLEL SIMULATION OF NETWORKS ON CHIP
    Marcus Eggenberger and Martin Radetzki

  2. PER-FLOW DELAY BOUND ANALYSIS BASED ON A FORMALIZED MICROARCHITECTURAL MODEL
    Xueqian Zhao and Zhonghai Lu
    Presentation Slides

  3. AN ACCURATE AND SCALABLE ANALYTIC MODEL FOR ROUND-ROBIN ARBITRATION IN NETWORK-ON-CHIP
    Erik Fischer and Gerhard P. Fettweis
    Presentation Slides

  4. PHYSICAL PLANNING FOR THE ARCHITECTURAL EXPLORATION OF LARGE-SCALE CHIP MULTIPROCESSORS (S)
    Javier De San Pedro, Nikita Nikitin, Jordi Cortadella and Jordi Petit
    Presentation Slides
11.10 -- 12.00 Poster Session 4
12.00 -- 1.30 Lunch
Courtyard West, Tempe Mission Palms (Symposium site)
1.30 -- 2.30 Session 5: Potpourri
Session Chair: Serag Gadelrab, Qualcomm
  1. ACCELERATING ATOMIC OPERATIONS ON THE GPU FOR BROADER APPLICABILITY
    Sean Franey and Mikko Lipasti
    Presentation Slides

  2. A SPECULATIVE ARBITER DESIGN TO ENABLE HIGH-FREQUENCY MANY-VC ROUTER IN NOCS
    Bo Zhao, Youtao Zhang and Jun Yang
    Presentation Slides

  3. QUADRISECTION-BASED TASK MAPPING ON MANY-CORE PROCESSORS FOR ENERGYEFFICIENT ON-CHIP COMMUNICATION (S)
    Nithin Michael, Yao Wang, Kevin Tang and Edward Suh
    Presentation Slides
2.30 -- 3.15 Poster Session 5 + Coffee Break
3.15 -- 5.15 Special Session on Emerging Interconnects Technologies

Organizers
Ahmed Louri, University of Arizona
Avinash Kodi, Ohio University

Panelists
Vijaykrishnan Narayanan, Pennsylvania State University
Kannan Raj, Oracle Labs
Sudhakar Yalamanchili, Georgia Tech
Partha Pande, Washington State University

More information available at the following link
6.30 -- 10.00 Banquet
Tempe Mission Palms (Symposium site)


Wednesday April 24, 2013 – NOCS Day 3

8.30 -- 9.30 Keynote Address
COMMUNICATION CHALLENGES IN ACCELERATOR-RICH ARCHITECTURES
Dr. Ravishankar Iyer,
Intel Corporation, Hillsboro, OR.

Abstract is at the following link
9.30 -- 9.45 Coffee Break
9.45 -- 11.00 Session 6: Network Architecture
Session Chair: Bin Li, Intel
  1. DYNAMIC TRAFFIC DISTRIBUTION AMONG HIERARCHY LEVELS IN HIERARCHICAL NETWORKS-ON-CHIP (NOCS)
    Ran Manevich, Israel Cidon and Avinoam Kolodny
    Presentation Slides

  2. CENTRALIZED BUFFER ROUTER: A LOW LATENCY, LOW POWER ROUTER FOR HIGH RADIX NOCS
    Syed Minhaj Hassan and Sudhakar Yalamanchili

  3. ON SELF-TUNING NETWORKS-ON-CHIP FOR DYNAMIC NETWORK-FLOW DOMINANCE ADAPTATION
    Xiaohang Wang, Terrence Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab and Maurizio Palesi
    Presentation Slides
11.00 -- 12.00 Poster Session 6 + Coffee Break
12.00 -- 12.30 Closing Session
Best Paper Award Announcement
12.30 -- 2.00 Lunch
Mellow Mushroom, 750 S. Mill Avenue, Suite #D100, Tempe, AZ 85281 (We will walk from the meeting room)