7th International Symposium on Networks-on-Chip
|April 22, 2013||8.30 -- 9.30||HETEROGENEOUS INTERCONNECTS FOR HETEROGENEOUS COMPUTING
Professor Luca Benini
University of Bologna, Bologna, Italy.
In an era of power-limited, memory-bound silicon, maximizing computational efficiency (GOPS/W/mm2) is key. Architectural heterogeneity is one of the most powerful approaches to gain silicon efficiency, but it comes at the price of reduced flexibility and complex non- portable software. In this talk I will discuss recent advances in interconnect architectures with associated design flows and software abstractions focusing on supporting architectural heterogeneity at multiple scales: from sub-system to multi-die.
|April 23, 2013||8.30 -- 9.30||UNDERSTANDING NETWORKS-ON-CHIP: A DECADE AND BEYOND
Professor Radu Marculescu
Carnegie Mellon University, Pittsburgh, PA.
During the past decade or so, we witnessed a major transition from computation- to communication-based design of integrated circuits and systems. Indeed, nowadays systems- on-chip (SoCs) represent true distributed systems at nanoscale where communication aspects dominate. Consequently, the network-on-chip (NoC) based architecture emerged as the de facto communication paradigm for multicore SoCs. However, in order to harness the huge potential offered by this new design paradigm, we need to reach beyond the established confines of digital design and (re)define a new science of NoC design.
Starting from these overarching ideas, in this talk, we discuss the theoretical foundations and practical implications of using the NoC approach to design the communication infrastructure of future thousand-core systems. Such a science of network design is crucial not only for understanding the main properties of network structure and behavior, but also for developing new mathematical models and tools needed to optimize and guide their practical implementation ranging from hardware, all the way up to software, and (user- aware) application development. Ultimately, the network concept can be also exploited in software, data centers, and cloud computing. So itís truly about science and engineering at their best.
|April 24, 2013||8.30 -- 9.30||COMMUNICATION CHALLENGES IN ACCELERATOR-RICH ARCHITECTURES
Dr. Ravishankar Iyer,
Intel Corporation, Hillsboro, OR.
To support rich usages at ultra-low power, architectures are evolving rapidly to integrate many domain-specific accelerators along with specialized cores as well as general-purpose cores on-die. Such accelerator-rich architectures pose new significant communication challenges for interconnects as well as cache/memory hierarchies. In this talk, I will describe some examples accelerator-rich architectures, the key challenges faced and outline potential solutions and research directions for the future. I will also describe challenges in benchmarks and performance evaluation for such architectures along the way.
Technology scaling into the sub-nanometer regime has offered unparalleled computation opportunity as future multi-core systems are projected to integrate 100s to 1000s of CPUs/GPUs on a single chip. With such a massive multi-core system, the focus of the academia/industry has shifted from being performance-bound computation-centric to power-bound communication-centric bringing the interconnect design to the forefront. While traditional metallic interconnects can provide the requisite bandwidth and deliver within latency boundaries, various Network-on-Chip (NoC) communication components (links, routers, channels, sockets) are fast consuming a vast majority of the power budget, thereby leaving insufficient power for computation. As power-crisis due to communication is fast becoming a major challenge, researchers are proposing alternate emerging technologies such as optical interconnects, wireless/RF interconnects and 3D interconnects to reduce the power burden of the communication fabric. While emerging technologies have the potential to deliver high performance/Watt, there are several critical technological barriers for wide-spread adoption.
To help address the promise as well as understand the technology hurdles of emerging technology, We invited four prominent speakers who will provide valuable insights into several of the emerging technologies proposed for Network-on-Chips (NoCs).
Ahmed Louri, University of Arizona
Avinash Kodi, Ohio University
Vijaykrishnan Narayanan, Pennsylvania State University
Kannan Raj, Oracle Labs
Sudhakar Yalamanchili, Georgia Tech
Partha Pande, Washington State University
Part I: Introductions: Special Session, Speakers (5-10 minutes)
Part II: Invited Presentations (4 presentations each of 20-25 minutes)
Part III-A: Answers to questions generated from the attendees ahead of time (selected by the organizers).
Part III-B: Questions from the audience attending the session.